In conventional CMOS (complementary metal oxide semiconductor) technology NMOS transistors are embedded in a p-type tub, and, conversely, PMOS transistors are embedded in an n-type tub. Each tub serves to isolate the transistors therein from the bulk substrate and from transistors in the other tub. However, the tubs should not be left floating; i.e., they should be connected to either V.sub.cc or to ground in order to prevent latch-up. For this purpose special conducting paths, known as tub-ties, establish ohmic connections between appropriate metal layers (the tub-tie contacts) and each of the tubs. Not every transistor needs a tub-tie, but every tub needs at least one tub-tie. Typically, the area of a tub-tie at the surface of the semiconductor is relatively small, measuring only about 1 .mu.m.times.1 .mu.m. In LOCOS (local oxidation of silicon) isolation of the tub-tie is formed in zones of silicon located between regions of isolating field oxide (FOX), whereas in STI (shallow trench isolation) it is formed in small pillars of silicon disposed between isolating oxide-filled trenches.
In standard CMOS front-end processing (i.e., processing up to but not including metalization), which usually entails about ten different photolithographic mask steps to fabricate the transistors, the source/drain (S/D) regions are typically doped heavily, whereas the tubs are only lightly doped. The tub-tie regions are also heavily doped, usually during the same ion implantation step that dopes the S/D regions. Doping of the n-type tub-tie region of the PMOS transistors, for example, is accomplished by opening a hole over the tub-tie location in the photoresist (PR) mask that protects the PMOS transistor locations during the n-type ion implantation of the S/D regions of the NMOS transistors. Conversely, doping of the p-type tub-tie region of the NMOS transistors is accomplished by opening a hole over the tub-tie location in the PR mask that protects the NMOS transistor locations during the p-type ion implantation of the S/D regions of the PMOS transistors.
However, IC fabrication processes which require a large number of PR mask steps are undesirable, in general implying lower yields and higher cost than processes which utilize fewer PR mask steps. Consequently, workers in the IC art have endeavored to reduce the number of PR mask steps required. See, for example, T. Horiuchi, U.S. Pat. No. 5,571,745 issued on Nov. 5, 1996, U. Schwalke et al., European Solid-State Device Research Conference, Conf Proc., pp. 317-320 (1996), and U. Schwalke et al, Symposium On VLSI Technology, Digest of Technical Papers, pp. 71-73 (1997). While the various prior art implementations differ, they all accomplish PR mask reduction by combining two or more implant steps, such as tub implants with gate implants. The most aggressive approach, which entails the largest cost reduction, combines all implants into a single PR mask step. However, in so doing the PR mask previously utilized to allow selective doping of the tub-tie regions is no longer available. Thus, a need remains in the art for a reduced-mask-count IC process that enables tub-tie regions to be formed.